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		<title>PHY405 Solutions</title>
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		<dc:creator><![CDATA[Admin_Louis]]></dc:creator>
		<pubDate>Sat, 05 Feb 2022 15:11:11 +0000</pubDate>
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					<description><![CDATA[<p>PHY405 Tma Solutions 1. In a AND gate where one of the inputs A is 0 and other input B are 1, the resulting output is 1 10 &#8212;&#62;&#62; 11 2. NOR gate is a combination of which gate NOR and NOT gate OR and AND gate NOR and NOT gate &#8212;&#62;&#62; OR and NOT [&#8230;]</p>
The post <a href="https://campusflava.com/blog/phy405-solutions/">PHY405 Solutions</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></description>
										<content:encoded><![CDATA[<p>PHY405 Tma Solutions</p>
<p>1. In a AND gate where one of the inputs A is 0 and other input B are 1, the resulting output is</p>
<p>1</p>
<p>10</p>
<p>&#8212;&gt;&gt;</p>
<p>11</p>
<p>2. NOR gate is a combination of which gate</p>
<p>NOR and NOT gate</p>
<p>OR and AND gate</p>
<p>NOR and NOT gate</p>
<p>&#8212;&gt;&gt; OR and NOT gate</p>
<p>3. NAND gate is a combination of which gate</p>
<p>NAND and NOT gate</p>
<p>AND and NOR gate</p>
<p>AND and NOT gate</p>
<p>&#8212;&gt;&gt; AND and NOT gate</p>
<p>4. If input to the circuit is 1, the output is 0 and if the input is 0 then the output is 1 is called</p>
<p>NOR gate circuit</p>
<p>&#8212;&gt;&gt; NOT gate circuit</p>
<p>NAND gate circuit</p>
<p>OR gate circuit</p>
<p>5. The NOT gate is also known as the</p>
<p>&#8212;&gt;&gt; Inverter</p>
<p>switch</p>
<p>Diode</p>
<p>PN juction diode</p>
<p>6. In a AND gate where both the inputs A and B are 1, the resulting output is</p>
<p>&#8212;&gt;&gt; 1</p>
<p>10</p>
<p>11</p>
<p>7. NOT gate circuit uses the cut-off and saturation modes of the</p>
<p>Diode</p>
<p>resistor</p>
<p>&#8212;&gt;&gt; transistor.</p>
<p>switch</p>
<p>8. In an OR gate where one of the inputs A is 0 and other input B are 1, the resulting output is</p>
<p>10</p>
<p>11</p>
<p>&#8212;&gt;&gt; 1</p>
<p>9. Electronically the AND gate can be realised by using</p>
<p>&#8212;&gt;&gt; two pn junction diodes</p>
<p>three pn junction diodes</p>
<p>two nn junction diodes</p>
<p>one pn junction diodes</p>
<p>10. Boolean algebra methodology includes the following except</p>
<p>The logic operations are written in the form of a Boolean expression.</p>
<p>From the given truth table, a Boolean expression can be obtained which may not represent a simple circuit having minimum number of gates.</p>
<p>The Boolean expression may then be simplified to get a digital circuit having minimum number of gates</p>
<p>&#8212;&gt;&gt; The Boolean expression may then be simplified to get a Analog circuit having maximum number of gates</p>
<p><strong>JOIN OUR TELEGRAM ON <a href="https://t.me/joinchat/kYg7RkDrjNQ0ZTA0">VIP NOUN UPDATES</a> – FOR FREE PHY405 PAST QUESTIONS AND EXAMS SUMMARIES</strong></p>The post <a href="https://campusflava.com/blog/phy405-solutions/">PHY405 Solutions</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></content:encoded>
					
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		<post-id xmlns="com-wordpress:feed-additions:1">71561</post-id>	</item>
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		<title>Boolean algebra methodology includes the following except</title>
		<link>https://campusflava.com/blog/boolean-algebra-methodology-includes-the-following-except/</link>
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		<dc:creator><![CDATA[Admin_Louis]]></dc:creator>
		<pubDate>Sat, 05 Feb 2022 15:09:20 +0000</pubDate>
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					<description><![CDATA[<p>Boolean algebra methodology includes the following except The logic operations are written in the form of a Boolean expression. From the given truth table, a Boolean expression can be obtained which may not represent a simple circuit having minimum number of gates. The Boolean expression may then be simplified to get a digital circuit having [&#8230;]</p>
The post <a href="https://campusflava.com/blog/boolean-algebra-methodology-includes-the-following-except/">Boolean algebra methodology includes the following except</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></description>
										<content:encoded><![CDATA[<p>Boolean algebra methodology includes the following except</p>
<p>The logic operations are written in the form of a Boolean expression.</p>
<p>From the given truth table, a Boolean expression can be obtained which may not represent a simple circuit having minimum number of gates.</p>
<p>The Boolean expression may then be simplified to get a digital circuit having minimum number of gates</p>
<p>&#8212;&gt;&gt; The Boolean expression may then be simplified to get a Analog circuit having maximum number of gates</p>The post <a href="https://campusflava.com/blog/boolean-algebra-methodology-includes-the-following-except/">Boolean algebra methodology includes the following except</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></content:encoded>
					
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		<post-id xmlns="com-wordpress:feed-additions:1">71560</post-id>	</item>
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		<title>Electronically the AND gate can be realised by using</title>
		<link>https://campusflava.com/blog/electronically-the-and-gate-can-be-realised-by-using/</link>
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		<dc:creator><![CDATA[Admin_Louis]]></dc:creator>
		<pubDate>Sat, 05 Feb 2022 15:09:12 +0000</pubDate>
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					<description><![CDATA[<p>Electronically the AND gate can be realised by using &#8212;&#62;&#62; two pn junction diodes three pn junction diodes two nn junction diodes one pn junction diodes</p>
The post <a href="https://campusflava.com/blog/electronically-the-and-gate-can-be-realised-by-using/">Electronically the AND gate can be realised by using</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></description>
										<content:encoded><![CDATA[<p>Electronically the AND gate can be realised by using</p>
<p>&#8212;&gt;&gt; two pn junction diodes</p>
<p>three pn junction diodes</p>
<p>two nn junction diodes</p>
<p>one pn junction diodes</p>The post <a href="https://campusflava.com/blog/electronically-the-and-gate-can-be-realised-by-using/">Electronically the AND gate can be realised by using</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></content:encoded>
					
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		<post-id xmlns="com-wordpress:feed-additions:1">71559</post-id>	</item>
		<item>
		<title>In an OR gate where one of the inputs A is 0 and other input B are 1, the resulting  output is</title>
		<link>https://campusflava.com/blog/in-an-or-gate-where-one-of-the-inputs-a-is-0-and-other-input-b-are-1-the-resulting-output-is/</link>
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		<dc:creator><![CDATA[Admin_Louis]]></dc:creator>
		<pubDate>Sat, 05 Feb 2022 15:09:06 +0000</pubDate>
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					<description><![CDATA[<p>In an OR gate where one of the inputs A is 0 and other input B are 1, the resulting output is 10 11 &#8212;&#62;&#62; 1</p>
The post <a href="https://campusflava.com/blog/in-an-or-gate-where-one-of-the-inputs-a-is-0-and-other-input-b-are-1-the-resulting-output-is/">In an OR gate where one of the inputs A is 0 and other input B are 1, the resulting  output is</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></description>
										<content:encoded><![CDATA[<p>In an OR gate where one of the inputs A is 0 and other input B are 1, the resulting output is</p>
<p>10</p>
<p>11</p>
<p>&#8212;&gt;&gt; 1</p>The post <a href="https://campusflava.com/blog/in-an-or-gate-where-one-of-the-inputs-a-is-0-and-other-input-b-are-1-the-resulting-output-is/">In an OR gate where one of the inputs A is 0 and other input B are 1, the resulting  output is</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></content:encoded>
					
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		<post-id xmlns="com-wordpress:feed-additions:1">71558</post-id>	</item>
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		<title>NOT gate  circuit uses the cut-off and saturation modes of the</title>
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		<dc:creator><![CDATA[Admin_Louis]]></dc:creator>
		<pubDate>Sat, 05 Feb 2022 15:09:00 +0000</pubDate>
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					<description><![CDATA[<p>NOT gate circuit uses the cut-off and saturation modes of the Diode resistor &#8212;&#62;&#62; transistor. switch</p>
The post <a href="https://campusflava.com/blog/not-gate-circuit-uses-the-cut-off-and-saturation-modes-of-the/">NOT gate  circuit uses the cut-off and saturation modes of the</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></description>
										<content:encoded><![CDATA[<p>NOT gate circuit uses the cut-off and saturation modes of the</p>
<p>Diode</p>
<p>resistor</p>
<p>&#8212;&gt;&gt; transistor.</p>
<p>switch</p>The post <a href="https://campusflava.com/blog/not-gate-circuit-uses-the-cut-off-and-saturation-modes-of-the/">NOT gate  circuit uses the cut-off and saturation modes of the</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></content:encoded>
					
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		<post-id xmlns="com-wordpress:feed-additions:1">71557</post-id>	</item>
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		<title>In a AND gate where both the inputs A and B are 1, the resulting output  is</title>
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		<dc:creator><![CDATA[Admin_Louis]]></dc:creator>
		<pubDate>Sat, 05 Feb 2022 15:08:52 +0000</pubDate>
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					<description><![CDATA[<p>In a AND gate where both the inputs A and B are 1, the resulting output is &#8212;&#62;&#62; 1 10 11</p>
The post <a href="https://campusflava.com/blog/in-a-and-gate-where-both-the-inputs-a-and-b-are-1-the-resulting-output-is/">In a AND gate where both the inputs A and B are 1, the resulting output  is</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></description>
										<content:encoded><![CDATA[<p>In a AND gate where both the inputs A and B are 1, the resulting output is</p>
<p>&#8212;&gt;&gt; 1</p>
<p>10</p>
<p>11</p>The post <a href="https://campusflava.com/blog/in-a-and-gate-where-both-the-inputs-a-and-b-are-1-the-resulting-output-is/">In a AND gate where both the inputs A and B are 1, the resulting output  is</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></content:encoded>
					
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		<post-id xmlns="com-wordpress:feed-additions:1">71556</post-id>	</item>
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		<title>The NOT gate is also known as the</title>
		<link>https://campusflava.com/blog/the-not-gate-is-also-known-as-the/</link>
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		<dc:creator><![CDATA[Admin_Louis]]></dc:creator>
		<pubDate>Sat, 05 Feb 2022 15:08:45 +0000</pubDate>
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					<description><![CDATA[<p>The NOT gate is also known as the &#8212;&#62;&#62; Inverter switch Diode PN juction diode Virus-free. www.avg.com</p>
The post <a href="https://campusflava.com/blog/the-not-gate-is-also-known-as-the/">The NOT gate is also known as the</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></description>
										<content:encoded><![CDATA[<p>The NOT gate is also known as the</p>
<p>&#8212;&gt;&gt; Inverter</p>
<p>switch</p>
<p>Diode</p>
<p>PN juction diode</p>
<table>
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</table>The post <a href="https://campusflava.com/blog/the-not-gate-is-also-known-as-the/">The NOT gate is also known as the</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></content:encoded>
					
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		<post-id xmlns="com-wordpress:feed-additions:1">71555</post-id>	</item>
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		<title>If input to the circuit is 1, the output is 0 and if the input is 0 then the output is 1 is called</title>
		<link>https://campusflava.com/blog/if-input-to-the-circuit-is-1-the-output-is-0-and-if-the-input-is-0-then-the-output-is-1-is-called/</link>
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		<dc:creator><![CDATA[Admin_Louis]]></dc:creator>
		<pubDate>Sat, 05 Feb 2022 15:08:35 +0000</pubDate>
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					<description><![CDATA[<p>If input to the circuit is 1, the output is 0 and if the input is 0 then the output is 1 is called NOR gate circuit &#8212;&#62;&#62; NOT gate circuit NAND gate circuit OR gate circuit</p>
The post <a href="https://campusflava.com/blog/if-input-to-the-circuit-is-1-the-output-is-0-and-if-the-input-is-0-then-the-output-is-1-is-called/">If input to the circuit is 1, the output is 0 and if the input is 0 then the output is 1 is called</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></description>
										<content:encoded><![CDATA[<p>If input to the circuit is 1, the output is 0 and if the input is 0 then the output is 1 is called</p>
<p>NOR gate circuit</p>
<p>&#8212;&gt;&gt; NOT gate circuit</p>
<p>NAND gate circuit</p>
<p>OR gate circuit</p>The post <a href="https://campusflava.com/blog/if-input-to-the-circuit-is-1-the-output-is-0-and-if-the-input-is-0-then-the-output-is-1-is-called/">If input to the circuit is 1, the output is 0 and if the input is 0 then the output is 1 is called</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></content:encoded>
					
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		<post-id xmlns="com-wordpress:feed-additions:1">71554</post-id>	</item>
		<item>
		<title>In a AND gate where one of the inputs A is 0 and other input B are 1, the resulting  output is</title>
		<link>https://campusflava.com/blog/in-a-and-gate-where-one-of-the-inputs-a-is-0-and-other-input-b-are-1-the-resulting-output-is/</link>
					<comments>https://campusflava.com/blog/in-a-and-gate-where-one-of-the-inputs-a-is-0-and-other-input-b-are-1-the-resulting-output-is/#respond</comments>
		
		<dc:creator><![CDATA[Admin_Louis]]></dc:creator>
		<pubDate>Sat, 05 Feb 2022 15:08:26 +0000</pubDate>
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					<description><![CDATA[<p>In a AND gate where one of the inputs A is 0 and other input B are 1, the resulting output is 1 10 &#8212;&#62;&#62; 11</p>
The post <a href="https://campusflava.com/blog/in-a-and-gate-where-one-of-the-inputs-a-is-0-and-other-input-b-are-1-the-resulting-output-is/">In a AND gate where one of the inputs A is 0 and other input B are 1, the resulting  output is</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></description>
										<content:encoded><![CDATA[<p>In a AND gate where one of the inputs A is 0 and other input B are 1, the resulting output is</p>
<p>1</p>
<p>10</p>
<p>&#8212;&gt;&gt;</p>
<p>11</p>The post <a href="https://campusflava.com/blog/in-a-and-gate-where-one-of-the-inputs-a-is-0-and-other-input-b-are-1-the-resulting-output-is/">In a AND gate where one of the inputs A is 0 and other input B are 1, the resulting  output is</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></content:encoded>
					
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		<post-id xmlns="com-wordpress:feed-additions:1">71553</post-id>	</item>
		<item>
		<title>NOR gate is a combination of which gate</title>
		<link>https://campusflava.com/blog/nor-gate-is-a-combination-of-which-gate/</link>
					<comments>https://campusflava.com/blog/nor-gate-is-a-combination-of-which-gate/#respond</comments>
		
		<dc:creator><![CDATA[Admin_Louis]]></dc:creator>
		<pubDate>Sat, 05 Feb 2022 15:08:16 +0000</pubDate>
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					<description><![CDATA[<p>NOR gate is a combination of which gate NOR and NOT gate OR and AND gate NOR and NOT gate &#8212;&#62;&#62; OR and NOT gate</p>
The post <a href="https://campusflava.com/blog/nor-gate-is-a-combination-of-which-gate/">NOR gate is a combination of which gate</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></description>
										<content:encoded><![CDATA[<p>NOR gate is a combination of which gate</p>
<p>NOR and NOT gate</p>
<p>OR and AND gate</p>
<p>NOR and NOT gate</p>
<p>&#8212;&gt;&gt; OR and NOT gate</p>The post <a href="https://campusflava.com/blog/nor-gate-is-a-combination-of-which-gate/">NOR gate is a combination of which gate</a> first appeared on <a href="https://campusflava.com">Campusflava</a>.]]></content:encoded>
					
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		<post-id xmlns="com-wordpress:feed-additions:1">71552</post-id>	</item>
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